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ds05-20838-1e fujitsu semiconductor data sheet flash memory cmos 2 m (256 k 8/128 k 16) bit mbm29f200ta -90-x/-12-x /MBM29F200BA -90-x/-12-x n features single 5.0 v read, program, and erase minimizes system level power requirements compatible with jedec-standard commands uses same software commands as e 2 proms compatible with jedec-standard world-wide pinouts 44-pin sop (package suf?: pf) 48-pin tsop (i) (package suf?: pftn ?normal bend type, pftr ?reversed bend type) minimum 100,000 write/erase cycles high performance 90 ns maximum access time sector erase architecture one 16k byte, two 8k bytes, one 32k byte, and three 64k bytes. any combination of sectors can be concurrently erased. also supports full chip erase. boot code sector architecture ta = top sector ba = bottom sector embedded erase tm algorithms automatically pre-programs and erases the chip or any sector embedded program tm algorithms automatically write and veri?s data at speci?d address data polling and toggle bit feature for detection of program or erase cycle completion ready/busy output (ry/by ) hardware method for detection of program of erase cycle completion. ?ow v cc write inhibit 3.2 v hardware reset pin resets internal state machine to the read mode. sector protection hardware method disables any combination of sectors from write or erase operations temporary sector groups unprotection hardware method temporarily enable any combination of sectors from write or erase operations (continued) embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
2 mbm29f200ta -90-x/-12-x /MBM29F200BA -90-x/-12-x (continued) erase suspend/resume suspends the erase operation to allow a read data in another sector within the same device extended operating temperature range: ?0 c to +85 c n package please refer to ?bm29f200ta/MBM29F200BA in detailed speci?ations. (fpt-44p-m16) (fpt-48p-m19) (fpt-48p-m20) 48-pin plastic tsop (i) 44-pin plastic sop marking side marking side marking side
3 mbm29f200ta -90-x/-12-x /MBM29F200BA -90-x/-12-x n general description the mbm29f200ta-x/ba-x is a 2m-bit, 5.0 v-only flash memory organized as 256k bytes of 8 bits each or 128k words of 16 bits each. the mbm29f200ta-x/ba-x is offered in a 44-pin sop and 48-pin tsop (i) packages. this device is designed to be programmed in-system with the standard system 5.0 v v cc supply. a 12.0 v v pp is not required for write or erase operations. the device can also be reprogrammed in standard eprom programmers. the mbm29f200ta-x/ba-x offers access times 90 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the device has separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the mbm29f200ta-x/ba-x is pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 12.0 v flash or eprom devices. the mbm29f200ta-x/ba-x is programmed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and veri?s proper cell margin. typically, each sector can be programmed and veri?d in about 0.5 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automatically times the erase pulse widths and veri?s proper cell margin. a sector is typically erased and veri?d in 1.0 second (if already completely preprogrammed.) the device also features a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the mbm29f200ta-x/ba-x is erased when shipped from the factory. the device features single 5.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , or the ry/by pin. once the end of a program or erase cycle has been completed, the device internally resets to the read mode. fujitsus flash technology combines years of eprom and e 2 prom experience to produce the highest levels of quality, reliability and cost effectiveness. the mbm29f200ta-x/ba-x memory electrically erases the entire chip or all bits within a sector simultaneously via fowler-nordhiem tunneling. the bytes/words are programmed one byte/word at a time using the eprom programming mechanism of hot electron injection.
4 mbm29f200ta -90-x/-12-x /MBM29F200BA -90-x/-12-x n flexible sector-erase architecture one 16k byte, two 8k bytes, one 32k byte, and three 64k bytes individual-sector, multiple-sector, or bulk-erase capability individual or multiple-sector protection is user de?able. n product line up part no. mbm29f200ta-x/MBM29F200BA-x ordering part no. v cc = 5.0 v 10% -90-x -12-x max. access time (ns) 90 120 max. ce access time (ns) 90 120 max. oe access time (ns) 35 50 1ffffh 1dfffh 1cfffh 1bfffh 17fffh 0ffffh 07fffh 00000h 3ffffh 3bfffh 39fffh 37fffh 2ffffh 1ffffh 0ffffh 00000h 16k byte 8k byte 8k byte 32k byte 64k byte 64k byte 64k byte mbm29f200ta-x sector architecture 3ffffh 2ffffh 1ffffh 0ffffh 07fffh 05fffh 03fffh 00000h 64k byte 64k byte 64k byte 32k byte 8k byte 8k byte 16k byte MBM29F200BA-x sector architecture 1ffffh 17fffh 0ffffh 07fffh 03fffh 02fffh 01fffh 00000h ( 8) ( 16) ( 8) ( 16)
5 mbm29f200ta -90-x/-12-x /MBM29F200BA -90-x/-12-x n block diagram ry/by buffer data latch y-gating cell matrix x-decoder y-decoder timer for program pulse/erase pulse low v cc detector ry/by address latch stb stb program voltage generator erase voltage generator input/output buffers chip enable output enable logic state control command register dq 0 to dq 15 we byte reset ce oe a 0 to a 16 a-1 v cc v ss
6 mbm29f200ta -90-x/-12-x /MBM29F200BA -90-x/-12-x n connection diagrams a 3 a 2 n.c. a 1 a 15 a 14 reset a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 oe dq 7 dq 6 dq 5 dq 14 dq 13 dq 12 dq 1 dq 0 a 0 a 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 44 43 42 41 mbm29f200ta-x/MBM29F200BA-x standard pinout tsop (i) fpt-48p-m19 (marking side) a 13 a 12 n.c. 17 18 19 20 36 35 34 33 40 39 38 37 v ss v ss v cc ry/by we 21 22 23 24 48 47 46 45 n.c. n.c. n.c. n.c. 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 41 42 43 44 45 46 47 48 29 30 31 32 mbm29f200ta-x/MBM29F200BA-x reverse pinout fpt-48p-m20 (marking side) 8 7 6 5 37 38 39 40 33 34 35 36 4 3 2 1 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 44 43 42 41 36 35 34 33 40 39 38 37 27 26 25 24 23 reset n.c. n.c. a 7 a 6 a 5 a 4 sop fpt-44p-m16 ce a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 we oe ry/by dq 7 dq 6 dq 12 dq 4 v cc a 0 a 1 a 2 a 3 dq 3 dq 2 dq 1 dq 0 v ss (top view) byte dq 15 /a -1 dq 4 dq 11 dq 3 dq 10 dq 2 dq 9 dq 8 ce oe dq 7 dq 6 dq 5 dq 14 dq 13 dq 12 dq 1 dq 0 a 0 a 16 v ss v ss v cc byte dq 15 /a -1 dq 4 dq 11 dq 3 dq 10 dq 2 dq 9 dq 8 ce a 3 a 2 n.c. a 1 a 15 a 14 reset a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 13 a 12 n.c. ry/by we n.c. n.c. n.c. n.c. dq 15 /a -1 dq 8 dq 9 dq 10 dq 11 a 16 byte v ss dq 14 dq 13 dq 5
7 mbm29f200ta -90-x/-12-x /MBM29F200BA -90-x/-12-x n logic symbol table 1 mbm29f200ta-x/MBM29F200BA-x pin con?uration pin function a -1 , a 0 to a 16 address inputs dq 0 to dq 15 data inputs/outputs ce chip enable oe output enable we write enable ry/by ready-busy output reset hardware reset pin/sector protection unlock byte selects 8-bit or 16-bit mode n.c. no internal connection v ss device ground v cc device power supply (5.0 v 10%) 17 a 0 to a 16 we oe ce dq 0 to dq 15 16 or 8 reset ry/by a -1 byte
8 mbm29f200ta -90-x/-12-x /MBM29F200BA -90-x/-12-x n ordering information industrial devices fujitsu industrial devices are available in several packages. the order number is formed by a combination of: mbm29f200 ta -90 pftn -x device number/description mbm29f200 2 mega-bit (256k 8-bit or 128k 16-bit) cmos flash memory 5.0 v-only read, program, and erase operating range industrial devices ambient temerature (t a ) = ?0 c to +85 c package type pftn = 48-pin thin small outline package (tsop) standard pinout pftr = 48-pin thin small outline package (tsop) reverse pinout pf = 44-pin small outline package speed option see product selector guide boot code sector architecture ta = top sector ba = bottom sector
9 mbm29f200ta -90-x/-12-x /MBM29F200BA -90-x/-12-x n absolute maximum ratings storage temperature .................................................................................................. ?5 c to +125 c ambient temperature with power applied................................................................... ?0 c to +85 c voltage with respect to ground all pins except a 9 , oe , reset (note 1).................. ?.0 v to +7.0 v v cc (note 1) ................................................................................................................ ?.0 v to +7.0 v a 9 , oe , reset (note 2) ............................................................................................. ?.0 v to +13.5 v notes: 1. minimum dc voltage on input or i/o pins is ?.5 v. during voltage transitions, inputs may negative overshoot v ss to ?.0 v for periods of up to 20 ns. maximum dc voltage on output and i/o pins is v cc +0.5 v. during voltage transitions, outputs may positive overshoot to v cc +2.0 v for periods of up to 20 ns. 2. minimum dc input voltage on a 9 , oe , reset pins are ?.5 v. during voltage transitions, a 9 , oe , reset pins may negative overshoot v ss to ?.0 v for periods of up to 20 ns. maximum dc input voltage on a 9 , oe , reset pins are +13.0 v which may positive overshoot to 13.5 v for periods of up to 20 ns. warning: stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. n recommended operating ranges industrial devices ambient temperature (t a ) .........................................................................?0 c to +85 c v cc supply voltages .....................................................................................+4.50 v to +5.50 v recommended operating ranges de?e those limits between which the functionality of the device is guaranteed.
10 mbm29f200ta -90-x/-12-x /MBM29F200BA -90-x/-12-x n maximum overshoot figure 1 maximum negative overshoot waveform +0.45 v ?.5 v 20 ns ?.0 v 20 ns 20 ns figure 2 maximum positive overshoot waveform 1 +2.0 v v cc +0.5 v 20 ns v cc +2.0 v 20 ns 20 ns figure 3 maximum positive overshoot waveform 2 v cc +0.5 v +13.0 v 20 ns +13.5 v 20 ns 20 ns note : this waveform is applied for a 9 , oe , and reset .
11 mbm29f200ta -90-x/-12-x /MBM29F200BA -90-x/-12-x n dc characteristics ttl/nmos compatible notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (at 6 mhz). the frequency component typically is 2 ma/mhz. 2. i cc active while embedded algorithm (program or erase) is in progress. parameter symbol parameter description test conditions min. max. unit i li input leakage current v in = v ss to v cc , v cc = v cc max. 1.0 m a i lo output leakage current v out = v ss to v cc , v cc = v cc max. 1.0 m a i lit a 9 , oe , reset inputs leakage current v cc = v cc max., a 9 , oe , reset = 12.0 v ?0 m a i cc1 v cc active current (note 1) ce = v il , oe = v ih byte 50 ma word 60 i cc2 v cc active current (note 2) ce = v il , oe = v ih ?0ma i cc3 v cc current (standby) v cc = v cc max., ce = v ih , reset = v ih 1.5 ma i cc4 v cc current (standby, reset) v cc = v cc max., reset = v il 1.5 ma v il input low level ?.5 0.6 v v ih input high level 2.4 v cc +0.5 v v id voltage for autoselect, sector protection, and temporary sector unprotection (a 9 , oe , reset ) v cc = 5.0 v 11.5 12.5 v v ol output low voltage level i ol = 5.8 ma, v cc = v cc min. 0.45 v v oh output high voltage level i oh = ?.5 ma, v cc = v cc min. 2.4 v v lko low v cc lock-out voltage 3.2 4.2 v
12 mbm29f200ta -90-x/-12-x /MBM29F200BA -90-x/-12-x cmos compatible notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (at 6 mhz). the frequency component typically is 2 ma/mhz. 2. i cc active while embedded algorithm (program or erase) is in progress. parameter symbol parameter description test conditions min. max. unit i li input leakage current v in = v ss to v cc , v cc = v cc max. 1.0 m a i lo output leakage current v out = v ss to v cc , v cc = v cc max. 1.0 m a i lit a 9 , oe , reset inputs leakage current v cc = v cc max. a 9 , oe , reset = 12.0 v ?0 m a i cc1 v cc active current (note 1) ce = v il , oe = v ih byte 50 ma word 60 i cc2 v cc active current (note 2) ce = v il , oe = v ih ?0ma i cc3 v cc current (standby) v cc = v cc max., ce = v cc 0.3 v, reset = v cc 0.3 v 100 m a i cc4 v cc current (standby, reset) v cc = v cc max., reset = v ss 0.3 v 100 m a v il input low level ?.5 0.6 v v ih input high level 0.7 v cc v cc +0.3 v v id voltage for autoselect, sector protection, and temporary sector unprotection (a 9 , oe , reset ) v cc = 5.0 v 11.5 12.5 v v ol output low voltage level i ol = 5.8 ma, v cc = v cc min. 0.45 v v oh1 output high voltage level i oh = ?.5 ma, v cc = v cc min. 0.85 v cc ? v oh2 i oh = ?00 m a, v cc = v cc min. v cc ?.4 v v lko low v cc lock-out voltage 3.2 4.2 v
13 mbm29f200ta -90-x/-12-x /MBM29F200BA -90-x/-12-x n ac characteristics read only operations characteristics note: test conditions- output load: 1 ttl gate and 100 pf input rise and fall times: 20 ns input pulse levels: 0.0 v to 3.0 v timing measurement reference level input: 0.45 v and 2.4 v output: 0.8 v and 2.0 v parameter symbols description test setup -90-x (note 1) -12-x (note 1) unit jedec standard t avav t rc read cycle time min. 90 120 ns t avqv t acc address to output delay ce = v il oe = v il max. 90 120 ns t elqv t ce chip enable to output delay oe = v il max. 90 120 ns t glqv t oe output enable to output delay max. 35 50 ns t ehqz t df chip enable to output high-z max. 20 30 ns t ghqz t df output enable to output high-z max. 20 30 ns t axqx t oh output hold time from addresses, ce or oe , whichever occurs first min. 0 0 ns ? ready reset pin low to read mode max. 20 20 m s t elfl t elfh ce or byte switching low or high max. 5 5 ns figure 4 test conditions c l 5.0 v diodes = in3064 or equivalent 2.7 k w device under test in3064 or equivalent 6.2 k w note: c l = 100 pf including jig capaciance
14 mbm29f200ta -90-x/-12-x /MBM29F200BA -90-x/-12-x write/erase/program operations alternate we controlled writes notes: 1. this does not include the preprogramming time. 2. these timings are for sector protection operations. parameter symbols description -90-x -12-x unit jedec standard t avav t wc write cycle time min. 90 120 ns t avwl t as address setup time min. 0 0 ns t wlax t ah address hold time min. 45 50 ns t dvwh t ds data setup time min. 45 50 ns t whdx t dh data hold time min. 0 0 ns ? oes output enable setup time min. 0 0 ns ? oeh output enable hold time read min. 0 0 ns toggle and data polling min. 10 10 ns t ghwl t ghwl read recover time before write min. 0 0 ns t elwl t cs ce setup time min. 0 0 ns t wheh t ch ce hold time min. 0 0 ns t wlwh t wp write pulse width min. 45 50 ns t whwl t wph write pulse width high min. 20 20 ns t whwh1 t whwh1 byte programming operation typ. 8 8 m s t whwh2 t whwh2 sector erase operation (note 1) typ. 1.5 1.5 sec max. 30 30 sec ? vcs v cc setup time min. 50 50 m s ? vlht voltage transition time (note 2) min. 4 4 m s ? wpp write pulse width (note 2) min. 100 100 m s ? oesp oe setup time to we active (note 2) min. 4 4 m s ? csp ce setup time to we active (note 2) min. 4 4 m s ? rp reset pulse width min. 500 500 ns ? flqz byte switching low to output high-z max. 30 30 ns ? busy program/erase valid to ry/by delay min. 35 50 ns
15 mbm29f200ta -90-x/-12-x /MBM29F200BA -90-x/-12-x write/erase/program operations alternate ce controlled writes note: this does not include the preprogramming time. parameter symbols description -90-x -12-x unit jedec standard t avav t wc write cycle time min. 90 120 ns t avel t as address setup time min. 0 0 ns t elax t ah address hold time min. 45 50 ns t dveh t ds data setup time min. 45 50 ns t ehdx t dh data hold time min. 0 0 ns ? oes output enable setup time min. 0 0 ns ? oeh output enable hold time read min. 0 0 ns toggle and data polling min. 10 10 ns t ghel t ghel read recover time before write min. 0 0 ns t wlel t ws we setup time min. 0 0 ns t ehwh t wh we hold time min. 0 0 ns t eleh t cp ce pulse width min. 45 50 ns t ehel t cph ce pulse width high min. 20 20 ns t whwh1 t whwh1 byte programming operation typ. 8 8 m s t whwh2 t whwh2 sector erase operation (note) typ. 1.5 1.5 sec max. 30 30 sec ? vcs v cc setup time typ. 50 50 m s ? rp reset pulse width min. 500 500 ns ? flqz byte switching low to output high-z max. 30 30 ns ? busy program/erase valid to ry/by delay min. 35 50 ns
16 mbm29f200ta -90-x/-12-x /MBM29F200BA -90-x/-12-x n erase and programming performance n tsop pin capacitance note: test conditions t a = 25 c, f = 1.0 mhz n sop pin capacitance note: test conditions t a = 25 c, f = 1.0 mhz parameter limits unit comments min. typ. max. sector erase time 1.5 30 sec excludes 00h programming prior to erasure byte programming time 8 500 m s excludes system-level overhead chip programming time 2.1 13 sec excludes system-level overhead erase/program cycle 100,000 cycles parameter symbol parameter description test setup typ. max. unit c in input capacitance v in = 0 8 9 pf c out output capacitance v out = 0 8 10 pf c in2 control pin capacitance v in = 0 8.5 11.5 pf parameter symbol parameter description test setup typ. max. unit c in input capacitance v in = 0 7.5 9 pf c out output capacitance v out = 0 8 10 pf c in2 control pin capacitance v in = 0 8.5 11 pf
17 mbm29f200ta -90-x/-12-x /MBM29F200BA -90-x/-12-x fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9702 ? fujitsu limited printed in japan all rights reserved. circuit diagrams utilizing fujitsu products are included as a means of illustrating typical semiconductor applications. com- plete information sufficient for construction purposes is not nec- essarily given. the information contained in this document has been carefully checked and is believed to be reliable. however, fujitsu as- sumes no responsibility for inaccuracies. the information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by fujitsu. fujitsu reserves the right to change products or specifications without notice. no part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu. the information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear con- trol systems or medical equipments for life support.

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